SystemVerilog mode
x
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// Literals
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1'b0
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1'bx
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1'bz
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16'hDC78
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'hdeadbeef
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'b0011xxzz
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1234
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32'd5678
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3.4e6
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128.7
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// Macro definition
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`define BUS_WIDTH 8;
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// Module definition
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module block(
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input clk,
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input rst_n,
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input [`BUS_WIDTH1:0] data_in,
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output [`BUS_WIDTH1:0] data_out
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);
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always @(posedge clk or negedge rst_n) begin
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if (rst_n) begin
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data_out < 8'b0;
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end else begin
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data_out < data_in;
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end
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if (rst_n)
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data_out < 8'b0;
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else
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data_out < data_in;
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if (rst_n)
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begin
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data_out < 8'b0;
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end
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else
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begin
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data_out < data_in;
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end
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end
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endmodule
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// Class definition
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class test;
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/**
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* Sum two integers
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*/
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function int sum(int a, int b);
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int result a b;
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string msg ("%d + %d = %d", a, b, result);
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(msg);
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return result;
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endfunction
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task delay(int num_cycles);
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repeat(num_cycles) #1;
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endtask
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endclass
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